This invention relates to managing signals in different clock domains and more particularly to a low gate count synchronizer circuit. This invention also relates to a low gate count programmable low-pass filter circuit.
Different clock signals are used to control different digital components on a circuit board. The different clock signals might operate in different clock domains. Clock signals operate in different clock domains when the clock signals are generated from independent sources. For example, a system clock might be generated from a clock circuit that is connected externally to a circuit board. A second reference clock might be generated locally on the circuit board with a crystal oscillator. The clock sources generate data signals that operate in different clock domains. The information that is to be passed between the two clock domain may be the data which is synchronized to the first clock, or the occurrence of the first clock itself.
Synchronizer circuits are used to prevent metastable conditions in devices that receive signals in different clock domains. The synchronizer circuits are located at each device requiring synchronization and typically synchronize the data to the clock signal driving the device. Complex synchronizer circuitry is necessary since a separate synchronizer circuit is needed for each device that requires synchronization and for each data line of each device.
Electrical lines often contain noise that can be mistakenly interpreted by digital circuitry as valid data. For example, network routers receive multiple network lines each carrying different signals. The signals on the network lines can be compromised by cross-talk and other noise conditions. If the noise is inadvertently processed as valid data, the router generates the wrong results or locks up.
Digital low pass filters can be used to remove noise from external serial data and clock lines. A standard circuit for filtering noise or "glitches" from a signal uses a counter that is run off a system clock. When an input signal is asserted, the counter samples the input signal at the system clock rate. A comparator compares the counter value to a predetermined threshold value. When the counter value reaches the threshold value, the comparator generates an output signal representing a filtered equivalent of the input signal. These filter circuits require 10-20 bit counters for each data bit and only work off one edge of the input signal. Thus, the filter circuitry is complex, has limited accuracy and requires a large number of data lines.
Noise often has different frequencies and amplitude characteristics in different operating environments. A low pass filter might be effective at removing noise having one type of frequency or amplitude characteristic but ineffective at filtering noise having another frequency or amplitude characteristic. Digital circuitry also has different sensitivity to signal noise. For example, one digital circuit may not be effected by small glitches in an input signal while another digital circuit might reboot from the same glitch. Therefore, some input signals require more rigorous filtering than other input signals.
Accordingly, a need remains for a simple synchronizer circuit that converts data and clock signals into different clock domains and a simple digital filter that can be programmed for different operating conditions.